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CMOS STATIC RAM 256K (32K x 8-BIT)
Integrated Device Technology, Inc.
IDT71256SA
FEATURES:
* 32K x 8 advanced high-speed CMOS static RAM * Commercial (0 to 70C) and Industrial (-40 to 85C) temperature options * Equal access and cycle times -- Commercial: 12/15/20/25ns -- Industrial: 15/20ns * One Chip Select plus one Output Enable pin * Bidirectional data inputs and outputs directly TTL-compatible * Low power consumption via chip deselect * Commercial product available in 28-pin 300- and 600-mil Plastic DIP, 300 mil Plastic SOJ and TSOP packages * Industrial product available in 28-pin 300 mil Plastic SOJ and TSOP packages
DESCRIPTION:
The ID71256SA is a 262,144-bit high-speed Static RAM organized as 32K x 8. It is fabricated using IDT's highperfomance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71256SA has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71256SA are TTLcompatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71256SA is packaged in 28-pin 300- and 600-mil Plastic DIP, 28-pin 300 mil Plastic SOJ and TSOP.
FUNCTIONAL BLOCK DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
ADDRESS DECODER 262,144-BIT MEMORY ARRAY
I/O 0 - I/O7 8
8
I/O CONTROL
2948 drw 01
CS WE OE
CONTROL LOGIC
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
(c)1997 Integrated Device Technology, Inc.
MAY 1997
DSC-2948/04
1
IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24
ABSOLUTE MAXIMUM RATINGS(1)
VCC
WE
Symbol VCC VTERM TBIAS TSTG PT IOUT
Rating Supply Voltage Relative to GND Terminal Voltage Relative to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Value -0.5 to +7.0 -0.5 to VCC+0.5 -55 to +125 -55 to +125 1.0 50
Unit V V C C W mA
SO28-5 P28-2 P28-1
23 22 21 20 19 18 17 16 15
A13 A8 A9 A11
OE
A10
CS
I/O7 I/O6 I/O5 I/O4 I/O3
2948 drw 02
DIP/SOJ TOP VIEW
OE
22 23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A 10
CS
NOTES: 2948 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
A 11 A9 A8 A 13
WE
V CC A 14 A 12 A7 A6 A5 A4 A3
SO28-8
I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
2948 drw 11
TRUTH TABLE(1,2)
CS OE WE
I/O DATAOUT DATAIN High-Z High-Z High-Z
Function Read Data Write Data Outputs Disabled Deselected -- Standby (ISB) Deselected -- Standby (ISB1)
2948 tbl 04
L L L H VHC (3)
L X H X X
H L H X X
TSOP TOP VIEW
NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
RECOMMENDED DC OPERATING CONDITIONS RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C GND 0V 0V VCC 4.5V to 5.5V 4.5V to 5.5V
3948 tbl 09
Symbol VCC GND VIH VIL
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage
Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. 5.5 0 VCC+0.5 0.8
Unit V V V V
NOTE: 2948 tbl 01 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V 10%
IDT71256SA Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min. -- -- -- 2.4 Max. 5 5 0.4 -- Unit A A V V
2948 tbl 05
2
IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC-0.2V)
Symbol ICC ISB ISB1 Parameter Dynamic Operating Current (2) CS VIL, Outputs Open, VCC = Max., f = fMAX Standby Power Supply Current (TTL Level) (2) CS VIH, Outputs Open, VCC = Max., f = fMAX Standby Power Supply Current (CMOS Level) (2) CS VHC, Outputs Open, VCC = Max., f = 0 VIN VLC or VIN VHC 71256SA12(3) 160 50 15 71256SA15 150 40 15 71256SA20 145 40 15 71256SA25(3) Unit 145 40 15 mA mA mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 3. Commercial temperature range only.
2948 tbl 06
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
2948 tbl 07
CAPACITANCE
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 7 Unit pF pF
NOTE: 2948 tbl 03 1. This parameter is guaranteed by device characterization, but not production tested.
5V 480 DATAOUT 30pF* 255
2948 drw 03
5V 480 DATAOUT 5pF* 255
2948 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
3
IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%)
71256SA12(2) Symbol Read Cycle tRC tAA tACS tCLZ tOE tOLZ tOH tPU
(1) (1) (1)
71256SA15 Min. 15 -- -- 4 0 -- 0 0 3 0 -- 15 10 10 0 10 0 7 0 4 0 Max. -- 15 15 -- 7 7 -- 6 -- -- 15 -- -- -- -- -- -- -- -- -- 6
71256SA20 Min. 20 -- -- 4 0 -- 0 0 3 0 -- 20 15 15 0 15 0 11 0 4 0 Max. -- 20 20 -- 10 10 -- 8 -- -- 20 -- -- -- -- -- -- -- -- -- 10
71256SA25(2) Min. 25 -- -- 4 0 -- 0 0 3 0 -- 25 20 20 0 20 0 13 0 4 0 Max. -- 25 25 -- 11 11 -- 10 -- -- 25 -- -- -- -- -- -- -- -- -- 11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2948 tbl 08
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power Up Time Chip Deselect to Power Down Time Write Cycle Time Address Valid to End of Write Chip Select to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Output Active from End of Write Write Enable to Output in High-Z
Min. 12 -- -- 4 0 -- 0 0 3 0 -- 12 9 9 0 9 0 6 0 4 0
Max. -- 12 12 -- 6 6 -- 6 -- -- 12 -- -- -- -- -- -- -- -- -- 6
tCHZ(1)
tOHZ(1)
tPD(1) tWC tAW tCW tAS tWP tWR tDW tDH tOW(1) tWHZ(1)
Write Cycle
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. Commercial temperature range only.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
tOE
CS
tOLZ
(5)
tACS tCLZ DATAOUT ICC ISB
(5)
(3)
tOHZ tCHZ
(5)
(5)
HIGH IMPEDANCE tPU
DATA OUT VALID tPD
VCC SUPPLY CURRENT
2948 drw 05
4
IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
2948 drw 06
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5) WE
tWC ADDRESS tAW
CS
tAS
WE
tWP(3)
tWR
tWHZ DATAOUT
(4)
(6)
tOW HIGH IMPEDANCE tDW tDH
(6)
tCHZ
(4)
(6)
DATAIN
DATAIN VALID
2948 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5) CS
tWC ADDRESS tAW
CS
tAS
WE
tCW
tWR
tDW DATAIN DATAIN VALID
tDH
2948 drw 08
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state.
5
IDT71256SA CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION - COMMERCIAL
IDT 71256 Device Type SA Power XX Speed XXX Package X Process/ Temperature Range
Blank
Commercial (0C to +70C)
P TP Y PZ
600-mil Plastic DIP (P28-1) 300-mil Plastic DIP (P28-2) 300-mil SOJ (SO28-5) TSOP Type I (SO28-8)
12 15 20 25
Speed in nanoseconds
2948 drw 09
ORDERING INFORMATION - INDUSTRIAL
IDT 71256 Device Type SA Power XX Speed XXX Package X Process/ Temperature Range
I
Industrial (-40C to +85C)
Y PZ
300-mil SOJ (SO28-5) TSOP Type I (SO28-8)
15 20
Speed in nanoseconds
2948 drw 10
6

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